1. Field of the Invention
The invention relates in general to the manufacturing of integrated circuits, and more particularly to a method of eliminating light reflection during exposure in photolithographic processing so as to prevent the occurrence of a bottle necking effect in polysilicon wires caused by a non-uniform thickness of a field oxide layer near its peripheral transition regions.
2. Description of the Related Art
Photolithography is an important procedure in the manufacture of semiconductors. Patterning on each thin film layer and on regions to which various impurities are applied, are generally defined using photolithographic techniques. Basically, photolithographic processing is begun by coating a layer of photosensitive material, commonly called photoresist, on the surface of a silicon wafer. Then, using a parallel light source, light is passed through a mask with a predefined pattern such that the photosensitive material is selectively exposed, thereby to transfer the pattern on the mask onto the photosensitive material. After that, the photo-reacted layer is developed and prepared for subsequent operations. In order to increase the resolution of the pattern, deep ultraviolet light (DUV) has recently been used as the light source. However, due to the comparatively shorter wavelength of the light, the effect of light reflection becomes more dominant, and as a result leads to more obvious pattern transfer errors and subsequent etching misalignments. An example is a caving-in along a portion of the line width of a polysilicon conductive wire, forming a so-called bottleneck.
In the manufacture of a dynamic random access memory (DRAM), due to a self-aligned contact window requirement, a cap layer composed of silicon dioxide or silicon nitride material is usually formed above a polysilicon layer to prevent short-circuiting between two neighboring polysilicon layers. When the level of integration is increased and the component dimensions are correspondingly reduced, for example, when the line width is smaller than 0.45 .mu.m the bottlenecking effect in the polysilicon conductive wire that occurs near the peripheral transition region of the field oxide layer due to light source reflection, becomes especially serious.
To better understand the pattern transfer errors generated by DUV light reflections, which result in the bottlenecking effect, an example illustrating the conventional method of forming a polysilicon conductive wire over a DRAM is given below.
FIGS. 1A through 1E are cross-sectional, perspective, and top views illustrating the steps of a conventional method of manufacturing a polysilicon conductive wire in a DRAM unit.
First, referring to FIG. 1A, a field oxide layer 12 for isolating a component as well as a necessary device (not shown in the Figure), are formed on a silicon substrate 10. Then, a polysilicon layer 14 is formed over the silicon substrate 10.
Referring next to FIG. 1B, a cap oxide layer 16 is formed above the polysilicon layer 14.
Referring next to FIG. 1C, the cap oxide layer 16 is coated with a photoresist layer 18.
Lastly, reference is made to FIG. 1D and 1E, which are perspective and top views of a structure formed after the application of photolithographic and etching processes to the structure shown in FIG. 1C. Using a parallel light source, such as a parallel source of DUV, light is passed through a patterned mask so that the pattern is transferred to the photoresist layer 18. Then, after development and partial removal of the photoresist layer 18, subsequent etching is performed which is targeted on regions without photoresist coverage. Consequently the cap oxide layer 16 and the polysilicon layer 14 are etched in sequence respectfully to form an etched cap oxide layer 16a and an etched polysilicon layer 14a. Finally, a double-layered composite structure of the cap oxide layer 16a and the etched polysilicon conducting wire 14a are formed upon removal of the residual photoresist layer 18.
In the aforementioned method of manufacturing polysilicon conductive wires in a DRAM unit, because of a difference in height the cap oxide layer running above the field oxide layer and crossing its peripheral transition region, ultraviolet light used in the selective exposure of the photoresist layer undergoes reflection upon reaching the surface of the cap oxide layer. This affects the photoresist layer below the supposed dark regions of the mask, and thus results in pattern transfer errors. Therefore, the etching performed thereafter leads to a partial over taking that results in a bottleneck structure in the wiring (polysilicon conductive wires).
Two conventional methods for reducing the bottlenecking effect caused by light reflection are generally used, namely:
(1) applying a top anti-reflection coating (T-ARC) above the photoresist layer; and PA1 (2) applying a bottom anti-reflection coating (B-ARC) before the application of the photoresist layer. Moreover, the first of these methods can be used for the prevention of the bottlenecking effect on specific locations only, and moreover its effectiveness is poor. Moreover, while the second of these methods can have the desirable effects, the repeatability of its etching process is poor, and the operation is hard to control. Further, the second method can cause formation of impurity particles that can severely affect the properties of the resulting device.